Fault-Tolerant learning in spiking astrocyte-neural networks on FPGAS

Anju P. Johnson, Junxiu Liu, Alan G. Millard, Shvan Karim, Andy M. Tyrrell, Jim Harkin, Jon Timmis, Liam McDaid, David M. Halliday

Allbwn ymchwil: Pennod mewn Llyfr/Adroddiad/Trafodion CynhadleddTrafodion Cynhadledd (Nid-Cyfnodolyn fathau)

5 Dyfyniadau(SciVal)

Crynodeb

The paper presents a neuromorphic system implemented on a Field Programmable Gate Array (FPGA) device establishing fault tolerance using a learning method, which is a combination of the Spike-Timing-Dependent Plasticity (STDP) and Bienenstock, Cooper, and Munro (BCM) learning rules. The rule modulates the synaptic plasticity level by shifting the plasticity window, associated with STDP, up/down the vertical axis as a function of postsynaptic neural activity. Specifically when neurons are inactive, either early on in the normal learning phase or when a fault occurs, the window is shifted up the vertical axis (open), leading to an increase in firing rate of the postsynaptic neuron. As learning progresses, the plasticity window moves down the vertical axis until the desired postsynaptic neuron firing rate is established. Experimental results are presented to show the effectiveness of the proposed approach in establishing fault tolerance. The system can maintain the network performance with at least one nonfaulty synapse. Finally, we discuss a robotic application utilizing the proposed architecture.

Iaith wreiddiolSaesneg
TeitlProceedings - 31st International Conference on VLSI Design, VLSID 2018 - Held concurrently with 17th International Conference on Embedded Systems, ES 2018
CyhoeddwrIEEE Press
Tudalennau49-54
Nifer y tudalennau6
ISBN (Electronig)9781538636923
Dynodwyr Gwrthrych Digidol (DOIs)
StatwsCyhoeddwyd - 27 Maw 2018
Digwyddiad31st International Conference on VLSI Design, VLSID 2018 - Pune, India
Hyd: 06 Ion 201810 Ion 2018

Cyfres gyhoeddiadau

EnwProceedings of the IEEE International Conference on VLSI Design
Cyfrol2018-January
ISSN (Argraffiad)1063-9667

Cynhadledd

Cynhadledd31st International Conference on VLSI Design, VLSID 2018
Gwlad/TiriogaethIndia
DinasPune
Cyfnod06 Ion 201810 Ion 2018

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