Homeostatic fault tolerance in spiking neural networks: A dynamic hardware perspective

Anju P. Johnson*, Junxiu Liu, Alan G. Millard, Shvan Karim, Andy M. Tyrrell, Jim Harkin, Jon Timmis, Liam J. McDaid, David M. Halliday

*Awdur cyfatebol y gwaith hwn

Allbwn ymchwil: Cyfraniad at gyfnodolynErthygladolygiad gan gymheiriaid

37 Dyfyniadau (Scopus)

Crynodeb

Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this paper, we propose a novel plastic neural network model, which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory interneurons, we develop a fault-resilient robotic controller implemented on an FPGA establishing obstacle avoidance task. We demonstrate the proposed methodology on a spiking neural network implemented on Xilinx Artix-7 FPGA. The system is able to maintain stable firing (tolerance ±10%) with a loss of up to 75% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware overhead with a tuning circuit (repair unit) which consumes only three slices/neuron for implementing a threshold voltage-based homeostatic fault-tolerant unit. The overall architecture has a minimal impact on power consumption and, therefore, supports scalable implementations. This paper opens a novel way of implementing the behavior of natural fault tolerant system in hardware establishing homeostatic self-repair behavior.

Iaith wreiddiolSaesneg
Rhif yr erthygl7995041
Tudalennau (o-i)687-699
Nifer y tudalennau13
CyfnodolynIEEE Transactions on Circuits and Systems I: Regular Papers
Cyfrol65
Rhif cyhoeddi2
Dynodwyr Gwrthrych Digidol (DOIs)
StatwsCyhoeddwyd - Chwef 2018

Ôl bys

Gweld gwybodaeth am bynciau ymchwil 'Homeostatic fault tolerance in spiking neural networks: A dynamic hardware perspective'. Gyda’i gilydd, maen nhw’n ffurfio ôl bys unigryw.

Dyfynnu hyn