Low power, dynamically reconfigurable, memoryless systolic array based architecture for Viterbi decoder

Conventional Viterbi decoder offers low throughput, consumes large power and utilizes large amount of on-chip (FPGA) resource. To overcome all these defects, a memory-less, low power, dynamically reconfigurable systolic array based Viterbi decoder is proposed. This architecture utilizes modified register exchange method which avoids the requirement of RAM for survivor path update. In addition, utilization of systolic array architecture introduces hardware concurrency, pipelining and parallelism which results in lower power consumption. This paper presents a prototype of Viterbi decoder with decode rate r = 1/2 and reconfigurable constraints length of K = 3, 4, 5, 6. This model is mapped on to Xilinx FPGA and tested using Xilinx system generator.