Low power, dynamically reconfigurable, memoryless systolic array based architecture for Viterbi decoder

A. K. Mishra*, P. P. Jiju

*Awdur cyfatebol y gwaith hwn

Allbwn ymchwil: Pennod mewn Llyfr/Adroddiad/Trafodion CynhadleddTrafodion Cynhadledd (Nid-Cyfnodolyn fathau)

Crynodeb

Conventional Viterbi decoder offers low throughput, consumes large power and utilizes large amount of on-chip (FPGA) resource. To overcome all these defects, a memory-less, low power, dynamically reconfigurable systolic array based Viterbi decoder is proposed. This architecture utilizes modified register exchange method which avoids the requirement of RAM for survivor path update. In addition, utilization of systolic array architecture introduces hardware concurrency, pipelining and parallelism which results in lower power consumption. This paper presents a prototype of Viterbi decoder with decode rate r = 1/2 and reconfigurable constraints length of K = 3, 4, 5, 6. This model is mapped on to Xilinx FPGA and tested using Xilinx system generator.

Iaith wreiddiolSaesneg
TeitlProceedings - 2011 International Conference on Energy, Automation and Signal, ICEAS - 2011
CyhoeddwrIEEE Press
Tudalennau379-383
Nifer y tudalennau5
ISBN (Electronig)978-1-4673-0136-7
ISBN (Argraffiad)978-1-4673-0137-4
Dynodwyr Gwrthrych Digidol (DOIs)
StatwsCyhoeddwyd - 28 Rhag 2011
Cyhoeddwyd yn allanolIe
Digwyddiad2011 International Conference on Energy, Automation and Signal, ICEAS - 2011 - Bhubaneswar, Odisha, India
Hyd: 28 Rhag 201130 Rhag 2011

Cyfres gyhoeddiadau

EnwProceedings - 2011 International Conference on Energy, Automation and Signal, ICEAS - 2011

Cynhadledd

Cynhadledd2011 International Conference on Energy, Automation and Signal, ICEAS - 2011
Gwlad/TiriogaethIndia
DinasBhubaneswar, Odisha
Cyfnod28 Rhag 201130 Rhag 2011

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