Multiplier-less floating point 1D DCT implementation

Gurkirat Singh*, Arun Kumar, Amit Kumar Mishra

*Awdur cyfatebol y gwaith hwn

Allbwn ymchwil: Pennod mewn Llyfr/Adroddiad/Trafodion CynhadleddTrafodion Cynhadledd (Nid-Cyfnodolyn fathau)

Crynodeb

Multimedia applications are becoming even more demanding. Hence, the next generation codecs invariably should be floating point compliant. With the field programmable gate arrays (FPGAs) technology getting mature, more and more signal processing applications are finding their niche in FPGAs. Current generation FPGAs have got hardware multipliers. However, these are general purpose multipliers and cannot be used for specific purposes. The present paper presents a novel FPGA implementation of one dimensional (8×1) point, multiplier less, floating point Discrete Cosine Transform. Distributed Arithmetic, parallelism and pipelining are exploited to produce a DCT implementation on a single FPGA. Two implementations are presented, one using single LUT and second using 2 parallel LUTs utilizing 68% and 89% area respectively with a maximum clock frequency of around 50MHz.

Iaith wreiddiolSaesneg
Teitl2008 IEEE Region 10 Conference, TENCON 2008
CyhoeddwrIEEE Press
Nifer y tudalennau6
ISBN (Argraffiad)1424424089, 9781424424085
Dynodwyr Gwrthrych Digidol (DOIs)
StatwsCyhoeddwyd - 19 Tach 2008
Cyhoeddwyd yn allanolIe
Digwyddiad2008 IEEE Region 10 Conference, TENCON 2008 - Hyderabad, India
Hyd: 19 Tach 200821 Tach 2008

Cyfres gyhoeddiadau

EnwIEEE Region 10 Annual International Conference, Proceedings/TENCON

Cynhadledd

Cynhadledd2008 IEEE Region 10 Conference, TENCON 2008
Gwlad/TiriogaethIndia
DinasHyderabad
Cyfnod19 Tach 200821 Tach 2008

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