An analog VLSI design for a neuron with a choice of learning rules

An analog implementation of a neuron using standard VLSI components is described. The node is capable of both delta-rule and simple error-correcting learning. Decomposition into functional blocks allows the parts of the design to be easily separated and understood. The connectivity problem is eased by serially encoding inputs so that all nodes in a layer are connected to a single line carrying activations from the previous layer. Performance implications of the architecture are considered. The design was simulated with the Spice transistor level simulator. Schemas for interconnection of large numbers of nodes and simulations of the circuitry required are presented. Results show that effective learning is achieved by both algorithms. Implementation of multiple learning rules in a single neuron is demonstrated as an effective way of increasing flexibility in neural network hardware implementations