TY - GEN
T1 - Fault-Tolerant learning in spiking astrocyte-neural networks on FPGAS
AU - Johnson, Anju P.
AU - Liu, Junxiu
AU - Millard, Alan G.
AU - Karim, Shvan
AU - Tyrrell, Andy M.
AU - Harkin, Jim
AU - Timmis, Jon
AU - McDaid, Liam
AU - Halliday, David M.
N1 - Funding Information:
The work is part of the SPANNER project and is funded by EPSRC grant(EP/N007050/1, EP/N00714X/1). Additionally, the authors would like to acknowledge the platform grant(EP/K040820/1) funded by EPSRC.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/3/27
Y1 - 2018/3/27
N2 - The paper presents a neuromorphic system implemented on a Field Programmable Gate Array (FPGA) device establishing fault tolerance using a learning method, which is a combination of the Spike-Timing-Dependent Plasticity (STDP) and Bienenstock, Cooper, and Munro (BCM) learning rules. The rule modulates the synaptic plasticity level by shifting the plasticity window, associated with STDP, up/down the vertical axis as a function of postsynaptic neural activity. Specifically when neurons are inactive, either early on in the normal learning phase or when a fault occurs, the window is shifted up the vertical axis (open), leading to an increase in firing rate of the postsynaptic neuron. As learning progresses, the plasticity window moves down the vertical axis until the desired postsynaptic neuron firing rate is established. Experimental results are presented to show the effectiveness of the proposed approach in establishing fault tolerance. The system can maintain the network performance with at least one nonfaulty synapse. Finally, we discuss a robotic application utilizing the proposed architecture.
AB - The paper presents a neuromorphic system implemented on a Field Programmable Gate Array (FPGA) device establishing fault tolerance using a learning method, which is a combination of the Spike-Timing-Dependent Plasticity (STDP) and Bienenstock, Cooper, and Munro (BCM) learning rules. The rule modulates the synaptic plasticity level by shifting the plasticity window, associated with STDP, up/down the vertical axis as a function of postsynaptic neural activity. Specifically when neurons are inactive, either early on in the normal learning phase or when a fault occurs, the window is shifted up the vertical axis (open), leading to an increase in firing rate of the postsynaptic neuron. As learning progresses, the plasticity window moves down the vertical axis until the desired postsynaptic neuron firing rate is established. Experimental results are presented to show the effectiveness of the proposed approach in establishing fault tolerance. The system can maintain the network performance with at least one nonfaulty synapse. Finally, we discuss a robotic application utilizing the proposed architecture.
KW - Astrocyte
KW - Bio-inspired Engineering
KW - Fault Tolerance
KW - Field Programmable Gate Array
KW - Neuromorphic Computing
KW - Self-Repair
KW - Spiking Neural Network
UR - http://www.scopus.com/inward/record.url?scp=85046737053&partnerID=8YFLogxK
U2 - 10.1109/VLSID.2018.36
DO - 10.1109/VLSID.2018.36
M3 - Conference Proceeding (Non-Journal item)
AN - SCOPUS:85046737053
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 49
EP - 54
BT - Proceedings - 31st International Conference on VLSI Design, VLSID 2018 - Held concurrently with 17th International Conference on Embedded Systems, ES 2018
PB - IEEE Press
T2 - 31st International Conference on VLSI Design, VLSID 2018
Y2 - 6 January 2018 through 10 January 2018
ER -