Hardware architecture for a bidirectional hetero-associative Protein Processing Associative Memory

Omer Qadir; Jerry Liu; Jon Timmis; Gianluca Tempesti; Andy Tyrrell

doi:10.1109/CEC.2011.5949620

Hardware architecture for a bidirectional hetero-associative Protein Processing Associative Memory

Omer Qadir^*, Jerry Liu, Jon Timmis, Gianluca Tempesti, Andy Tyrrell

^*Corresponding author for this work

Department of Computer Science

University of York

Research output: Chapter in Book/Report/Conference proceeding › Conference Proceeding (Non-Journal item)

8 Citations (Scopus)

Abstract

This paper details an extension to an architecture for robust bidirectional hetero-associative recall. Our proposed Protein Processor Associative Memory (PPAM) is fundamentally different from the traditional processing methods which use arithmetic operations and consequently Arithmetic and Logic Units (ALUs). In this paper, we improve on our initial work addressing concerns surrounding hardware implementation. We present the improved computational architecture, coupled with a corresponding hardware architecture for implementation. Results of applying the hardware implementation on a small dataset are included, along with reports from synthesis tools about hardware utilisation.

Original language	English
Title of host publication	2011 IEEE Congress of Evolutionary Computation, CEC 2011
Publisher	IEEE Press
Pages	208-215
Number of pages	8
ISBN (Print)	9781424478347
DOIs	https://doi.org/10.1109/CEC.2011.5949620
Publication status	Published - 2011
Event	2011 IEEE Congress of Evolutionary Computation, CEC 2011 - New Orleans, LA, United States of America Duration: 05 Jun 2011 → 08 Jun 2011

Publication series

Name	2011 IEEE Congress of Evolutionary Computation, CEC 2011

Conference

Conference	2011 IEEE Congress of Evolutionary Computation, CEC 2011
Country/Territory	United States of America
City	New Orleans, LA
Period	05 Jun 2011 → 08 Jun 2011

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10.1109/CEC.2011.5949620

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Qadir, O., Liu, J., Timmis, J., Tempesti, G., & Tyrrell, A. (2011). Hardware architecture for a bidirectional hetero-associative Protein Processing Associative Memory. In 2011 IEEE Congress of Evolutionary Computation, CEC 2011 (pp. 208-215). Article 5949620 (2011 IEEE Congress of Evolutionary Computation, CEC 2011). IEEE Press. https://doi.org/10.1109/CEC.2011.5949620

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title = "Hardware architecture for a bidirectional hetero-associative Protein Processing Associative Memory",

abstract = "This paper details an extension to an architecture for robust bidirectional hetero-associative recall. Our proposed Protein Processor Associative Memory (PPAM) is fundamentally different from the traditional processing methods which use arithmetic operations and consequently Arithmetic and Logic Units (ALUs). In this paper, we improve on our initial work addressing concerns surrounding hardware implementation. We present the improved computational architecture, coupled with a corresponding hardware architecture for implementation. Results of applying the hardware implementation on a small dataset are included, along with reports from synthesis tools about hardware utilisation.",

author = "Omer Qadir and Jerry Liu and Jon Timmis and Gianluca Tempesti and Andy Tyrrell",

year = "2011",

doi = "10.1109/CEC.2011.5949620",

language = "English",

isbn = "9781424478347",

series = "2011 IEEE Congress of Evolutionary Computation, CEC 2011",

publisher = "IEEE Press",

pages = "208--215",

booktitle = "2011 IEEE Congress of Evolutionary Computation, CEC 2011",

address = "United States of America",

note = "2011 IEEE Congress of Evolutionary Computation, CEC 2011 ; Conference date: 05-06-2011 Through 08-06-2011",

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Qadir, O, Liu, J, Timmis, J, Tempesti, G & Tyrrell, A 2011, Hardware architecture for a bidirectional hetero-associative Protein Processing Associative Memory. in 2011 IEEE Congress of Evolutionary Computation, CEC 2011., 5949620, 2011 IEEE Congress of Evolutionary Computation, CEC 2011, IEEE Press, pp. 208-215, 2011 IEEE Congress of Evolutionary Computation, CEC 2011, New Orleans, LA, United States of America, 05 Jun 2011. https://doi.org/10.1109/CEC.2011.5949620

Hardware architecture for a bidirectional hetero-associative Protein Processing Associative Memory. / Qadir, Omer; Liu, Jerry; Timmis, Jon et al.
2011 IEEE Congress of Evolutionary Computation, CEC 2011. IEEE Press, 2011. p. 208-215 5949620 (2011 IEEE Congress of Evolutionary Computation, CEC 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference Proceeding (Non-Journal item)

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AB - This paper details an extension to an architecture for robust bidirectional hetero-associative recall. Our proposed Protein Processor Associative Memory (PPAM) is fundamentally different from the traditional processing methods which use arithmetic operations and consequently Arithmetic and Logic Units (ALUs). In this paper, we improve on our initial work addressing concerns surrounding hardware implementation. We present the improved computational architecture, coupled with a corresponding hardware architecture for implementation. Results of applying the hardware implementation on a small dataset are included, along with reports from synthesis tools about hardware utilisation.

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Y2 - 5 June 2011 through 8 June 2011

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Hardware architecture for a bidirectional hetero-associative Protein Processing Associative Memory

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