TY - JOUR
T1 - Homeostatic fault tolerance in spiking neural networks
T2 - A dynamic hardware perspective
AU - Johnson, Anju P.
AU - Liu, Junxiu
AU - Millard, Alan G.
AU - Karim, Shvan
AU - Tyrrell, Andy M.
AU - Harkin, Jim
AU - Timmis, Jon
AU - McDaid, Liam J.
AU - Halliday, David M.
N1 - Funding Information:
Manuscript received March 27, 2017; revised June 16, 2017; accepted July 5, 2017. Date of publication July 28, 2017; date of current version January 25, 2018. The work is part of the SPANNER project and is funded by EPSRC grant (EP/N007050/1, EP/N00714X/1). Additionally, the authors would like to acknowledge the platform grant (EP/K040820/1) funded by EPSRC. This paper was recommended by Associate Editor A. Cilardo. (Corresponding author: Anju P. Johnson.) A. P. Johnson, A. G. Millard, A. M. Tyrrell, J. Timmis, and D. M. Halliday are with the Intelligent Systems & Nano-science Research Group, Department of Electronic Engineering, University of York, York YO10 5DD, U.K. (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2018/2
Y1 - 2018/2
N2 - Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this paper, we propose a novel plastic neural network model, which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory interneurons, we develop a fault-resilient robotic controller implemented on an FPGA establishing obstacle avoidance task. We demonstrate the proposed methodology on a spiking neural network implemented on Xilinx Artix-7 FPGA. The system is able to maintain stable firing (tolerance ±10%) with a loss of up to 75% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware overhead with a tuning circuit (repair unit) which consumes only three slices/neuron for implementing a threshold voltage-based homeostatic fault-tolerant unit. The overall architecture has a minimal impact on power consumption and, therefore, supports scalable implementations. This paper opens a novel way of implementing the behavior of natural fault tolerant system in hardware establishing homeostatic self-repair behavior.
AB - Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this paper, we propose a novel plastic neural network model, which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory interneurons, we develop a fault-resilient robotic controller implemented on an FPGA establishing obstacle avoidance task. We demonstrate the proposed methodology on a spiking neural network implemented on Xilinx Artix-7 FPGA. The system is able to maintain stable firing (tolerance ±10%) with a loss of up to 75% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware overhead with a tuning circuit (repair unit) which consumes only three slices/neuron for implementing a threshold voltage-based homeostatic fault-tolerant unit. The overall architecture has a minimal impact on power consumption and, therefore, supports scalable implementations. This paper opens a novel way of implementing the behavior of natural fault tolerant system in hardware establishing homeostatic self-repair behavior.
KW - bio-inspired engineering
KW - dynamic partial reconfiguration
KW - fault tolerance
KW - FPGA
KW - homeostasis
KW - mixed-mode clock manager
KW - phase locked loop
KW - Self-repair
UR - https://www.scopus.com/pages/publications/85028947387
U2 - 10.1109/TCSI.2017.2726763
DO - 10.1109/TCSI.2017.2726763
M3 - Article
AN - SCOPUS:85028947387
SN - 1549-8328
VL - 65
SP - 687
EP - 699
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 2
M1 - 7995041
ER -