Low power, dynamically reconfigurable, memoryless systolic array based architecture for Viterbi decoder

A. K. Mishra*, P. P. Jiju

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference Proceeding (Non-Journal item)

Abstract

Conventional Viterbi decoder offers low throughput, consumes large power and utilizes large amount of on-chip (FPGA) resource. To overcome all these defects, a memory-less, low power, dynamically reconfigurable systolic array based Viterbi decoder is proposed. This architecture utilizes modified register exchange method which avoids the requirement of RAM for survivor path update. In addition, utilization of systolic array architecture introduces hardware concurrency, pipelining and parallelism which results in lower power consumption. This paper presents a prototype of Viterbi decoder with decode rate r = 1/2 and reconfigurable constraints length of K = 3, 4, 5, 6. This model is mapped on to Xilinx FPGA and tested using Xilinx system generator.

Original languageEnglish
Title of host publicationProceedings - 2011 International Conference on Energy, Automation and Signal, ICEAS - 2011
PublisherIEEE Press
Pages379-383
Number of pages5
ISBN (Electronic)978-1-4673-0136-7
ISBN (Print)978-1-4673-0137-4
DOIs
Publication statusPublished - 28 Dec 2011
Externally publishedYes
Event2011 International Conference on Energy, Automation and Signal, ICEAS - 2011 - Bhubaneswar, Odisha, India
Duration: 28 Dec 201130 Dec 2011

Publication series

NameProceedings - 2011 International Conference on Energy, Automation and Signal, ICEAS - 2011

Conference

Conference2011 International Conference on Energy, Automation and Signal, ICEAS - 2011
Country/TerritoryIndia
CityBhubaneswar, Odisha
Period28 Dec 201130 Dec 2011

Keywords

  • Constraint length
  • FPGA
  • register-exchange method
  • systolic array

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