Low power, dynamically reconfigurable, memoryless systolic array based architecture for Viterbi decoder

A. K. Mishra*, P. P. Jiju

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference Proceeding (Non-Journal item)

Fingerprint

Dive into the research topics of 'Low power, dynamically reconfigurable, memoryless systolic array based architecture for Viterbi decoder'. Together they form a unique fingerprint.

Computer Science