Multiplier-less floating point 1D DCT implementation

Gurkirat Singh*, Arun Kumar, Amit Kumar Mishra

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference Proceeding (Non-Journal item)

Abstract

Multimedia applications are becoming even more demanding. Hence, the next generation codecs invariably should be floating point compliant. With the field programmable gate arrays (FPGAs) technology getting mature, more and more signal processing applications are finding their niche in FPGAs. Current generation FPGAs have got hardware multipliers. However, these are general purpose multipliers and cannot be used for specific purposes. The present paper presents a novel FPGA implementation of one dimensional (8×1) point, multiplier less, floating point Discrete Cosine Transform. Distributed Arithmetic, parallelism and pipelining are exploited to produce a DCT implementation on a single FPGA. Two implementations are presented, one using single LUT and second using 2 parallel LUTs utilizing 68% and 89% area respectively with a maximum clock frequency of around 50MHz.

Original languageEnglish
Title of host publication2008 IEEE Region 10 Conference, TENCON 2008
PublisherIEEE Press
Number of pages6
ISBN (Print)1424424089, 9781424424085
DOIs
Publication statusPublished - 19 Nov 2008
Externally publishedYes
Event2008 IEEE Region 10 Conference, TENCON 2008 - Hyderabad, India
Duration: 19 Nov 200821 Nov 2008

Publication series

NameIEEE Region 10 Annual International Conference, Proceedings/TENCON

Conference

Conference2008 IEEE Region 10 Conference, TENCON 2008
Country/TerritoryIndia
CityHyderabad
Period19 Nov 200821 Nov 2008

Keywords

  • Codecs
  • DCT
  • Distributed arithmetic
  • Floating point notation
  • FPGAs

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